Verilog Modelsim 程序问题——1位全加器源文件module adder(sum,co,cin,x,y);input x,y,cin;output sum,co;assign {co,sum}=x+y+cin;endmodule 测试文件`timescale 1ns/10psmodule adder_test;reg x,y,cin;wire sum,co;initial beginx=0;y=0;cin=0;#1
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![Verilog Modelsim 程序问题——1位全加器源文件module adder(sum,co,cin,x,y);input x,y,cin;output sum,co;assign {co,sum}=x+y+cin;endmodule 测试文件`timescale 1ns/10psmodule adder_test;reg x,y,cin;wire sum,co;initial beginx=0;y=0;cin=0;#1](/uploads/image/z/13831039-55-9.jpg?t=Verilog+Modelsim+%E7%A8%8B%E5%BA%8F%E9%97%AE%E9%A2%98%E2%80%94%E2%80%941%E4%BD%8D%E5%85%A8%E5%8A%A0%E5%99%A8%E6%BA%90%E6%96%87%E4%BB%B6module+adder%28sum%2Cco%2Ccin%2Cx%2Cy%29%3Binput+x%2Cy%2Ccin%3Boutput+sum%2Cco%3Bassign+%7Bco%2Csum%7D%3Dx%2By%2Bcin%3Bendmodule+%E6%B5%8B%E8%AF%95%E6%96%87%E4%BB%B6%60timescale+1ns%2F10psmodule+adder_test%3Breg+x%2Cy%2Ccin%3Bwire+sum%2Cco%3Binitial+beginx%3D0%3By%3D0%3Bcin%3D0%3B%231)
Verilog Modelsim 程序问题——1位全加器源文件module adder(sum,co,cin,x,y);input x,y,cin;output sum,co;assign {co,sum}=x+y+cin;endmodule 测试文件`timescale 1ns/10psmodule adder_test;reg x,y,cin;wire sum,co;initial beginx=0;y=0;cin=0;#1
Verilog Modelsim 程序问题——1位全加器
源文件
module adder(sum,co,cin,x,y);
input x,y,cin;
output sum,co;
assign {co,sum}=x+y+cin;
endmodule
测试文件
`timescale 1ns/10ps
module adder_test;
reg x,y,cin;
wire sum,co;
initial
begin
x=0;y=0;cin=0;
#100 x=1;y=0;cin=0;
#100 x=0;y=1;cin=0;
#100 x=1;y=1;cin=0;
#100 x=0;y=0;cin=1;
#100 x=1;y=0;cin=1;
#100 x=0;y=1;cin=1;
#100 x=1;y=1;cin=1;
end
endmodule
最后的波形里面的结果问什么一直是高阻 没有结果?程序哪错了?
Verilog Modelsim 程序问题——1位全加器源文件module adder(sum,co,cin,x,y);input x,y,cin;output sum,co;assign {co,sum}=x+y+cin;endmodule 测试文件`timescale 1ns/10psmodule adder_test;reg x,y,cin;wire sum,co;initial beginx=0;y=0;cin=0;#1
你的激励文件跟你的源文件完全没有关联,结果必然是这样