vHdl程序分析 (5 DOWNTO 0); 表示什么ARCHITECTURE Behavioral OF FIFO ISTYPE fifo_array IS ARRAY(0 TO 4095) OF STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL fifo_memory :fifo_array; SIGNAL full_flag :STD_LOGIC; SIGNAL empty_flag :STD_LOGIC; SIGNAL read_a
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![vHdl程序分析 (5 DOWNTO 0); 表示什么ARCHITECTURE Behavioral OF FIFO ISTYPE fifo_array IS ARRAY(0 TO 4095) OF STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL fifo_memory :fifo_array; SIGNAL full_flag :STD_LOGIC; SIGNAL empty_flag :STD_LOGIC; SIGNAL read_a](/uploads/image/z/10059090-42-0.jpg?t=vHdl%E7%A8%8B%E5%BA%8F%E5%88%86%E6%9E%90+%285+DOWNTO+0%29%3B+%E8%A1%A8%E7%A4%BA%E4%BB%80%E4%B9%88ARCHITECTURE+Behavioral+OF+FIFO+ISTYPE+fifo_array+IS+ARRAY%280+TO+4095%29+OF+STD_LOGIC_VECTOR%289+DOWNTO+0%29%3B+SIGNAL+fifo_memory+%3Afifo_array%3B+SIGNAL+full_flag+%3ASTD_LOGIC%3B+SIGNAL+empty_flag+%3ASTD_LOGIC%3B+SIGNAL+read_a)
vHdl程序分析 (5 DOWNTO 0); 表示什么ARCHITECTURE Behavioral OF FIFO ISTYPE fifo_array IS ARRAY(0 TO 4095) OF STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL fifo_memory :fifo_array; SIGNAL full_flag :STD_LOGIC; SIGNAL empty_flag :STD_LOGIC; SIGNAL read_a
vHdl程序分析 (5 DOWNTO 0); 表示什么
ARCHITECTURE Behavioral OF FIFO IS
TYPE fifo_array IS ARRAY(0 TO 4095) OF STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL fifo_memory :fifo_array;
SIGNAL full_flag :STD_LOGIC;
SIGNAL empty_flag :STD_LOGIC;
SIGNAL read_addr :STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL write_addr :STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL counter :STD_LOGIC_VECTOR(5 DOWNTO 0);
vHdl程序分析 (5 DOWNTO 0); 表示什么ARCHITECTURE Behavioral OF FIFO ISTYPE fifo_array IS ARRAY(0 TO 4095) OF STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL fifo_memory :fifo_array; SIGNAL full_flag :STD_LOGIC; SIGNAL empty_flag :STD_LOGIC; SIGNAL read_a
这个是申明6位的一个 STD_LOGIC_VECTOR,